The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer (i.e., M layers) in a selective recess region.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices and conductive interconnect layers are fabricated in and on a single wafer. The conductive interconnect layers serve as a network of pathways that transport signals throughout an integrated circuit (IC), thereby connecting circuit components of the IC into a functioning whole and to the outside world. Interconnect layers are themselves interconnected by a network of holes (or vias) formed through the wafer. As IC feature sizes continue to decrease, the aspect ratio (i.e., the ratio of height/depth to width) of features such as vias generally increases. Fabricating intricate structures of conductive interconnect layers and vias within an increasingly smaller wafer footprint is one of the most process-intensive and cost-sensitive portions of semiconductor IC fabrication.